This paper focuses on the effect of heterogeneous cache hierarchy in data center processors in the dark silicon era. For extreme-scale high performance computing systems, system-wide power consumption has been identified as one of the key constraints. As energy consumpt
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This paper focuses on the effect of heterogeneous cache hierarchy in data center processors in the dark silicon era. For extreme-scale high performance computing systems, system-wide power consumption has been identified as one of the key constraints. As energy consumption becomes a key issue for operation and maintenance of cloud data centers, cloud computing providers are becoming significantly concerned. Emerging non-volatile memory technologies are favorable replacement for conventional memory. Here, we employ a nonvolatile memory called spin-transfer torque random access memory (STT-RAM) as an on-chip L2 cache to obtain lower energy compared to conventional L2 caches, like SRAM. High density, fast read access, near-zero leakage power and non-volatility make STT-RAM a significant technology for on-chip memories. In order to decrease memory energy consumption, it is required to address both the leakage and dynamic energy. Previous studies have mainly studied specific schemes based on common applications and do not provide a thorough analysis of emerging scale-out applications with multiple design options. Here, we discuss different outlooks consisting of performance and energy efficiency in cloud processors by running CloudSuite benchmarks as one of scale-out workloads. Experiment results on the CloudSuite benchmarks show that using STT-RAM memory compare to SRAM memory as last level cache, consumes less energy in L2 cache, around 59% at maximum.
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